What is high-speed counter

What is a high-speed counter?

Counting fast pulses without missing events

A high-speed counter (HSC) is a function or device that uses dedicated counting hardware to track closely spaced digital pulses. It may be built into a PLC, provided by a separate counter module or implemented as a standalone panel instrument. Applications include position tracking, product counting, length measurement and speed calculation. Its permissible speed depends on the input circuitry, counting mode and model.

Editor's note: An HSC counts incoming digital pulses. In PLC terminology, PWM and PTO are separate output functions concerned with pulse generation. Suitable hardware can measure the frequency of a PWM signal, but this does not make PWM the counter's fundamental counting method. The HSC discussed here performs hardware-based digital counting.

How does it differ from a normal PLC counter?

In many applications, an ordinary program counter processes input changes observed while the program executes. Input-module updates, input filtering and the program cycle affect whether a transition is observed. For example, a 10 kHz signal has a 100 µs period; 50 pulses can arrive within 5 ms. Reading the input only once per cycle cannot distinguish all those pulses.

With supported inputs and settings, HSC hardware continues counting without requiring the cyclic program to observe every pulse individually. The program reads the accumulated value. Adding software rising-edge detection cannot recover pulses that were never captured. Correct pulse acquisition and the time at which the PLC acts on that value are separate considerations.

Single-channel counting, direction and A/B encoders

Single-channel operation counts the selected pulse edges. Depending on the device, available modes may include pulse plus direction, separate up/down inputs or A/B quadrature. The phase sequence between an encoder's A and B channels allows a compatible counter to determine movement direction.

For an incremental encoder, ×1, ×2 and ×4 evaluation define which edges are counted. In ×4 mode, both rising and falling edges of A and B are evaluated. An encoder producing 1,024 complete pulse periods per revolution on channel A therefore provides 4,096 counts/revolution in this mode. With suitable configuration, the Z channel can provide a reference or capture event; it does not make an incremental system inherently absolute.

How is the required input frequency calculated?

For P pulse periods per revolution on channel A and speed n in rpm, use fA = P × n / 60. With 1,024 PPR at 3,000 rpm, the channel-A frequency is 51,200 Hz. With ×4 evaluation, the resulting count-event rate becomes 204,800 counts/s.

Check whether a catalog's “kHz” figure specifies the signal frequency per channel or the decoded counting rate. Limits may differ between single-channel and A/B operation, channel configurations and electrical interfaces. Also check how the manufacturer defines PPR and CPR: a stated encoder resolution may already include fourfold evaluation.

Why does electrical input compatibility matter?

First match the encoder output type to the counter's input circuitry. NPN and PNP connections, common terminals and signal voltages cannot be treated as interchangeable. TTL and HTL levels also require compatible inputs. An encoder's supply voltage does not mean its output always switches at that same voltage.

A compatible line-driver encoder and differential receiver can improve signal integrity, particularly in electrically noisy environments. Voltage, cable, termination and connection requirements must still follow the manufacturer's documentation. A and B channels must not be confused with their complementary signals, and signal-cable routing must account for interference from power and motor cables.

How do filtering and pulse width interact?

An input filter that rejects short interference pulses may also reject valid pulses. At 50 kHz and a 50% duty cycle, the period is 20 µs, with 10 µs at each high and low level. A millisecond-scale filter applied to the input used by the HSC can prevent such a signal from being counted. Check the minimum ON and OFF durations as well as the average frequency.

The shortest filter setting is not always appropriate either: interference or mechanical contact bounce can create extra counts. Choose the setting from the actual waveform and the manual's limits. A photoelectric sensor's response time or an inductive sensor's switching frequency may also be the limiting factor. A fast counter cannot create pulses that the sensor fails to produce.

Converting counts into distance and speed

If travel per encoder revolution is C, channel-A resolution is P and the evaluation factor is k, the ideal conversion is distance = count × C / (P × k). With C = 200 mm, P = 1,024 and k = 4, one count represents approximately 0.0488 mm of travel. This is digital resolution, not mechanical accuracy. Slip, backlash, measuring-wheel diameter and encoder errors also matter.

Speed can be calculated from the count difference over a defined interval or from the device's supported frequency/period measurement. A shorter measurement interval provides faster updates, but at low speed the small number of pulses can make the displayed value more stepped. Consider the measurement interval, time base and filtering together.

Capture, comparison and overflow handling

Where supported, capture/latch stores the count in hardware at a specified input event. Hardware comparison or a high-speed output can provide more deterministic threshold response than a check in the cyclic program. These functions are not available on every HSC. Fast counting does not mean that a relay or mechanical system responds at the same speed.

Commissioning checks include dedicated input assignments, counting mode, direction, reset, initial value and filters. Establish the counter bit width, signed/unsigned data type, overflow behavior and power-loss retention from the manual. If scaling is wrong by exactly a factor of four, inspect the evaluation factor. If counts are lost only at higher speed, investigate pulse width, filtering, sensor performance and wiring.

Related topics

Continue with the PLC side: High-speed pulse output is a separate function from counting incoming pulses. Ladder programming explains processing the count, the PLC CPU handles program execution, and PLC debugging supports commissioning checks. When comparing PLC brands and models, compare HSC channels and mode-dependent limits too.

Other equipment groups: Encoders supply movement information, tachometers measure rotational speed, and power supplies establish supply conditions. HMI panels display the value to the operator; display refresh rate is different from counting-hardware speed. Standalone counters can provide counting, preset and scaling functions outside a PLC.

Counter and tachometer models and prices

Sources

Rockwell Automation: ControlLogix High-speed Counter Module: Counting and frequency modes, input filters and capture functions.

Schneider Electric: M221 High Speed Counter: HSC configuration, counting modes, thresholds and reflex outputs.

OMRON: NX-series High-speed Counter Unit Specifications: Input interfaces, channel configurations and mode-dependent counting limits.

Beckhoff: Basic Function Principles: A/B phases, fourfold evaluation and referencing.

OMRON: Open Collector and Line Driver for High-speed Counters: Electrical interface compatibility and noise immunity.